This invention relates to a transmission apparatus for carrying out transmission of digital data, and a method therefor.
As the interface standard which has supported high speed data transfer and real time transfer with a view to realization of interface for data transfer, IEEE 1394 high performance serial bus standard (hereinafter referred to as IEEE 1394 standard) is known.
In this IEEE 1394 standard, data transfer rates (speeds) at 100 Mbps (98.304 Mbps), 200 Mbps (196.608 Mbps) and 400 Mbps (393.216 Mbps) are prescribed. The 1394 port having high order transfer rate is prescribed so as to hold compatibility with the low order transfer rate thereof. Thus, data transfer rates of 100 Mbps, 200 Mbps and 400 Mbps can exist in mixed state on the same network. Moreover, in the IEEE 1394 standard, as shown in FIG. 1, there is employed transfer format of the DS-Link (Data/Strobe Link) coding system such that transfer data is converted into two signals of data signal and strobe signal for compensating that signal to take Exclusive logical sum of these two signals so that clock can be generated. Further, as the cable structure is shown in the cross sectional view of FIG. 2, there is prescribed a cable 200 of the structure in which the entirety of cable in which two sets of twist pair lines (signal lines) 202 shielded by respective first shield layers 201 and power lines 203 are bundled is further shielded by a second shield layer 204.
Moreover, in the connection system in the IEEE 1394 standard, two kinds of systems of the daisy chain and the node branch can be used. In the daisy chain system, 16 nodes (equipment having the 1394 port) at the maximum can be connected and the longest distance between respective nodes is set to 4.5 m. As shown in FIG. 3, by using the node branch in combination, as far as 63 nodes (physical node addresses) which is the maximum in the standard can be connected.
Further, in .the IEEE 1394 standard, plug-in/plug-out of the cable of the structure as described above can be carried out in the state where the equipment is operative, i.e., the state where power is turned ON. At the time point when node is supplemented on deleted, reconstruction of the 1394 network is automatically carried out. At this time, equipments of the connected nodes can be automatically recognized, and IDs and/or arrangement of the connected equipments are caused to undergo management on the interface.
The components and the protocol architecture of the interface in conformity with the IEEE 1394 standard are shown in FIG. 4. The interface of the IEEE 1394 standard can be classified into hardware and firmware.
The hardware consists of physical layer (PHY) and link layer.
Further, in the physical layer, signal of the IEEE 1394 standard is directly driven. In addition, the link layer comprises interface between host interface and physical layer.
The firmware consists of transaction layer consisting of management driver for carrying out actual operation with respect to interface in conformity with the IEEE 1394 standard and management layer consisting of driver for management of network in conformity with the IEEE 1394 standard which is called SBM (Serial Bus Management).
Further, application layer consists of software that user uses and management software which interfaces with the transaction layer or the management layer.
In the IEEE 1394 standard, transfer operation carried out within the network is called subaction and the following two kinds of subactions are prescribed. Namely, as two subactions, the asynchronous transfer mode called xe2x80x9casynchronousxe2x80x9d and synchronous transfer mode which has guaranteed transfer band called xe2x80x9cisochronousxe2x80x9d are defined. Further, respective subactions are classified into the following three parts to take transfer states called xe2x80x9carbitrationxe2x80x9d, xe2x80x9cpacket transmissionxe2x80x9d and xe2x80x9cacknowledgmentxe2x80x9d.
In the asynchronous subaction, the asynchronous transfer is carried out. In FIG. 5 showing the transition state in point of time in this transfer mode, the first subaction gap indicates the idle state of bus. By monitoring time of this subaction gap, whether or not new transfer can be carried out after transfer immediately before is completed is judged.
Further, when idle state of predetermined time or more lasts, the node which desires to carry out transfer judges that the bus can be used to execute arbitration for acquiring the control right of bus. In practice, judgment of stop of bus is carried out by node B positioned at the route as shown in FIGS. 6(a), (b). The node which has obtained the control right of bus by such arbitration then executes transfer of data, i.e., packet transmission. After the data transfer, the node which has received data executes responsive acknowledgment by sending back of ack (sending back code for confirmation of reception) corresponding to that reception result with respect to the transferred data. By execution of this acknowledgment, it can be confirmed by the content of the ack that transfer has been normally carried out along with transmission and reception nodes.
Thereafter, the system state returns to the subaction gap, i.e., idle state of bus for a second time. Thus, transfer operation as described above is repeated.
Moreover, in the isochronous subaction, transfer of the structure similar to the asynchronous transfer is essentially carried out. As shown in FIG. 7, transfer in this case is executed preferentially to the asynchronous transfer at the asynchronous subaction. The isochronous transfer in this isochronous subaction is executed preferentially to the asynchronous transfer at the asynchronous subaction every about 8 kHz, thereby resulting in the transfer mode which has guaranteed transfer band. Thus, transfer of real time data is realized.
In the case of carrying out isochronous transfer of real time data at plural nodes at the same time, channel ID for distinguishing the content (sending node) is set at that transfer data to receive only necessary real time data.
The physical layer in the IEEE 1394 standard as described above consists, as shown in FIG. 8, for example, of a physical layer logic block (PHY LOGIC) 102, a selector block (RXCLOCK/DATA SELECTOR) 103, respective port logic blocks (PORT LOGIC 1, PORT LOGIC 2, PORT LOGIC 3) 104, 105, 106, respective cable ports (CABLE PORT 1, CABLE PORT 2, CABLE PORT 3) 107, 108, 109, and a clock generating block (PLL) 110.
The physical layer logic block 102 serves to carry out I/O control and arbitration control to and from link layer in the IEEE 1394 standard, and is connected to a link layer controller 100 and is connected to the selector block 103 and the respective port logic blocks 104, 105, 106.
The selector block 103 serves to carry out selection of data (DATA1, DATA2, DATA3) and their receiving clocks (RXCLK1, RXCLK2, RXCLK3) received through logic blocks 104, 105, 106 connected to the respective cable ports 107, 108, 109, and is connected to the physical layer logic block 102 and the respective port logic blocks 104, 105, 106.
In the case of transmission of data, this selector block 103 sends, to all port logic blocks 104, 105, 106, packet data (DATA) sent from the physical layer logic block 102. Moreover, in the case of reception, the selector block 103 selects one set of packet data (DATA1, DATA2, DATA3) and their receiving clocks (RXCLK1, RXCLK2, RXCLK3) received through the respective port logic blocks 104, 105, 106 to send, to the physical layer logic block 102, packet data and their receiving clocks received through the cable ports 107, 108, 109. For example, in the case where the selector block 103 selects packet data (DATA1) and its receiving clock (RXCLK1) received through the port logic block 104, the selector block 103 sends, to the physical layer logic block 102, packet data (DATA1) and its receiving clock (RXCLK1) that the port logic block 104 has received through the cable port 107. Then, packet data selected by the selector block 103 is written into FIFO memory within the physical layer logic block 102 by its receiving clock. The packet data which has been written into this FIFO memory is read out by system clock (SYSCLK) given by the clock generating block 110.
The port logic block 104 serves to carry out transmission/reception of arbitration signal (ARB.SIGNAL) and data (DATA1) through the cable port 107, and has a function to generate receiving clock (RXCLK1) from data signal and its strobe signal sent through the cable port 107. Moreover, at the time of arbitration, arbitration signal (ARB.SIGNAL) is sent from the physical layer logic block 102 to the port logic block 104.
Further, at the time of transmission of data, this port logic block 104 converts packet data (DATA1) sent through the selector block 103 from the physical layer logic block 102 into serial data by transmitting clock (TXCLK) given by the clock generating block 110 to transmit it from the cable port 107.
In addition, at the time of reception of data, this port logic block 104 sends, to the physical layer logic block 102 through the selector block 103, packet data (DATA1) received through the cable port 107 along with its receiving clock (RXCLK1). Further, in the case where this port logic block 104 is selected by the selector block 103, packet data (DATA1) is written into FIFO memory within the physical layer logic block 102 by its receiving clock (RXCLK1).
The port logic block 105 serves to carry out transmission/reception of arbitration signal (ARB.SIGNAL) and data (DATA2) through the cable port 108, and has a function to generate receiving clock (RXCLK2) from data signal and its strobe signal sent through the cable port 108. In addition, at the time of arbitration, arbitration signal (ARB.SIGNAL) is sent from the physical layer logic block 102 to the port logic block 105.
Further, at the time of transmission of data, this port logic block 105 converts packet data (DATA2) sent through the selector block 103 from the physical layer logic block 102 into serial data by transmitting clock (TXCLK) given by the clock generating block 110 to transmit it from the cable port 108.
Further, at the time of reception of data, this port logic block 105 sends packet data (DATA2) received through the cable port 108 to the physical layer logic block 102 through the selector block 103 along with its receiving clock (RXCLK2). Further, in the case where this port logic block 105 is selected by the selector block 103, packet data (DATA2) is written into FIFO memory within the physical layer logic block 102 by its receiving clock RXCLK2.
The port logic block 106 serves to carry out transmission/reception of arbitration signal (ARB.SIGNAL) and data (DATA3) through the cable port 109, and has a function to generate receiving clock (RXCLK3) from data signal and its strobe signal sent through the cable port 109. In addition, at the time of arbitration, arbitration signal (ARB.SIGNAL) is sent from the physical layer logic block 102 to the port logic block 106.
Further, at the time of transmission of data, this logic block 106 converts packet data (DATA3) sent through the selector block 103 from the physical layer logic block 102 into serial data by transmitting clock (TXCLK) given by the clock generating block 110 to transmit it from the cable port 109.
Further, at the time of reception of data, this port logic block 106 sends, to the physical layer logic block 102 through the selector block 103, packet data (DATA3) received through the cable port 109 along with its receiving clock (RXCLK3). In addition, in the case where this port logic block 104 is selected by the selector block 103, packet data (DATA1) is written into FIFO memory within the physical layer logic block 102 by its receiving clock (RXCLK1).
The cable port 107 drives the twist pair cable by signal sent from the port logic block 104, and carries out level conversion of signal sent through the twist pair cable to send it to the port logic block 104.
The cable port 108 drives the twist pair cable by signal sent from the port logic block 105, and carries out level conversion of signal sent through the twist pair cable to send it to the port logic block 105.
The cable port 109 drives the twist pair cable by signal sent from the port logic block 106, and carries out level conversion of signal sent through the twist pair cable to send it to the port logic block 106.
The clock generating block 110 generates system clock (SYSCLK) of 49.152 MHz and transmitting clock (TXCLK) of 98.304 MHz from clock of 24.576 MHz given by a crystal oscillator 111.
The logical values of the arbitration signal in the physical layer is ternary (values) of xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9cZxe2x80x9d. These ternary values are generated in accordance with the rule shown in the following Tables 1 and 2, and are decoded by the rule shown in Table 3. In this case, the value xe2x80x9cZxe2x80x9d indicates inoperative state of driver.
In this case, the first set of twist pair lines TPA/TPA of two sets of twist pair lines 202 transmit strobe signal (Strb_Tx), and receive data signal(Data_Rx). On the other hand, the second set of twist pair lines TPB/TPB* transmit data signal (Data_Tx) and receive strobe signal (Strb_Rx). The Strb_Tx signal, the Data_Tx signal, Strb_Enable signal and Data_Enable signal are used for generating arbitration signals (Arb_A_Rx, Arb_B_Rx).
Moreover, in the physical layer, the rule shown in the following Table 4 is used to encode two transmission arbitration signals (Arb_A_Tx, Arb_B_Tx) so that they are placed in line state. As shown in the Table 4, these states have meanings different in dependency upon whether corresponding signal is sent to the parent node or the child node.
The parent/child relationship in the IEEE 1394 standard will now be described. Among plural nodes connected to the network, there exist several nodes positioned at the ends (leaves). Immediately after bus reset, respective nodes judge whether or not the nodes themselves are leaves. Judgments as to whether or not respective nodes are leaves are carried out by recognizing how many cables are connected to respective corresponding nodes. Namely, node having only one port or node to which only one cable is connected even if it has plural ports will be leaf. Respective leaves carry out inquiry with respect to node of destination of connection (parent node). The node which has received the inquiry allows the node from which inquiry has been issued, connected to the port to which inquiry has been issued to be child to further carry out inquiry with respect to destination of connection from the port in which the parent/child relation has been not yet determined. In this way, the parent/child relationship within the network is determined. Ultimately, the node in which all ports have been caused to be parent serves as route.
In the physical layer, interpolation arbitration signal (Arb_A, Arb_B) is decoded on the basis of the rule shown in the following Table 5 so that it is placed in line state.
In the above-described IEEE 1394 standard, there is provided the condition necessary as interface which connects or links civil equipments which handle image to computer. Accordingly, in general homes, various equipments such as audio equipment, visual equipment or personal computer, etc. are connected with ease by single cable, thereby making it possible to construct the network within the home. Thus, it becomes possible to operate various equipments with ease.
However, in the above-mentioned IEEE 1394 standard, since the distance between equipments to be connected, i.e., cable length between nodes is prescribed so that it is 4.5 m at the maximum, when attempt is made to construct network extending over, e.g., plural rooms even within the home, a large number of nodes only required for junction of cable must be provided.
In addition, when attempt is made to extend cable length without changing the system of the physical layer in the IEEE 1394 standard, cable must be thickened. As a result, not only working efficiency of laying (drawing) of cable for network, etc. is lowered, but also the cable itself becomes expensive.
In view of actual circumstances of the prior art as described above, an object of this invention is to provide an interface apparatus for digital serial data which has realized extension of cable length between nodes in the digital serial data interface which carries out arbitration of bus use right prior to transfer of data so that long distance transmission can be made.
This invention is directed to a data transmission apparatus which carries out transmission/reception of data and control codes, which comprises an input/output port, data converting processing means for converting data to be transmitted from n bit code to m bit code to output it to the input/output port, and for converting data received from the input/output port from m bit code to n bit code, and control signal converting processing means for converting a transmit control signal for acquiring use right of a transmission path connected to the input/output port into control code consisting of m bit code except for the m bit code allocated (assigned) to data to output it to the input/output port, and for converting control code of m bits received from the input/output port into a control signal.
In addition, this invention is directed to a data transmission method for carrying out transmission/reception of data and control code, which comprises a transmit data converting processing step of converting data to be transmitted from n bit code to m bit code to output it to an input/output port, receive data converting processing step of converting data received from the input/output port from m bit code to n bit code, a transmit control signal converting step of converting a transmit control signal for acquiring use right of a transmission path connected to the input/output port into control code consisting of m bit code except for m bit code allocated to data, and a receive control signal converting processing step of converting control code of m bits received from the input/output port into a control signal.